An asynchronous state machine, by definition, changes from a current state to a next state based on its present state and the condition of signals from external devices indicating the states of these devices. For proper operation of the state machine, the signals must be conditioned, that is, transitioned, in a particular order and/or combination. If, for example, a given signal is asserted late or released early, it may cause the state machine to change to an unintended next state.
In a system of interest, asynchronous state machines are employed in transactions between modules on a bus referred to as the "Futurebus+." A transaction follows a "compelled" protocol in which one or more modules operating as slaves must provide to a module operating as a bus master various acknowledgement, or handshake, signals throughout the operation. When the master receives these signals it proceeds to the next stage of the operation. The compelled protocol is described in IEEE Standard 896, the Futurebus+ standard, which is incorporated herein by reference.
Every compelled transaction on the Futurebus+includes a connection phase and a disconnection phase and may or may not include a data phase between the connection and disconnection phases. Each phase involves specific asynchronous, or compelled, communications between the designated bus master module and one or more slave module(s). The data phase is segmented into a number of "beats," where a beat includes the transition, that is, assertion or release, of a synchronization line by a master followed by the release of an appropriate acknowledge line by the slave(s). Between the transitions of the various synchronization and acknowledge lines, the bus master and slaves place data on, and capture data from, the bus.
During a first beat and subsequent "odd" beats of a compelled write operation, for example, a master sends command information and (write) data over the bus and asserts a data synchronization line DS. The participating slaves then capture the command information and (write) data, place status information on the bus and release an appropriate acknowledgement line. During a second or subsequent "even" data beat the master captures the slave status information, sends to the slaves the next (write) data and releases the data synchronization line DS. The slaves then capture the data, place status information on the bus and release an appropriate acknowledgement line. When the master senses the release of the acknowledgement line, it starts the next beat of the operation.
The master continues to assert and release the data synchronization line DS whenever it places (write) data on the bus and the slaves continue to release acknowledgement lines whenever they place status information on the bus. If a compelled read operation is being performed, the slaves send (read) data to the master with the status information before releasing their acknowledgement lines, the master captures the (read) data and sends command information and data synchronization assertions or releases to the slaves, which direct the slaves to send additional data.
If the bus master and slaves do not assert and release their synchronization and acknowledgement signals in the proper order and do not properly coordinate their data transmissions and data capture operations with the appropriate synchronization and acknowledgement signals, the data transfer operation may not complete and the bus may therefore "hang", which means that the various modules will each be waiting either for a next transition on an acknowledge line or a next transition on a synchronization line, and thus, none of the modules can transition to a next operation step.